The present invention is generally related to integrated circuit devices and their processing for the manufacture of semiconductor devices. More particularly, the present invention provides a method for forming a surrounding stacked gate fin field effect transistor (fin FET) structure nonvolatile memory device.
As semiconductor memory devices become increasingly integrated, the feature size including the channel length of individual devices is gradually reduced. This causes a short channel effect and also increases the junction leakage current. Leakage current was not a significant problem in the past, but it has become more serious concern now that transistor gates and other chip components measure only a few atoms thick. In a notebook computer, leakage current means short battery life and in a server computer, it means higher power bills. Also, in a nonvolatile memory device, the leakage current leads to degradation of data retention time and other electrical characteristics as the device feature size is reduced.
To solve these problems, fin field effect transistors (fin FETs) that have fin-shaped silicon active regions have been introduced. Among other things, the fin-shaped silicon active region typically enables multi-gate FET devices. For example, a conducting region (e.g., gate region) wraps around the fin-shaped silicon structure. Since a gate electrode is formed on the fin active region, a fin FET may use an entire face of a projected-portion as a channel. Thus, the channel length is often sufficient to prevent or substantially reduce the short channel effect. Such a fin FET can effectively control a leakage current generated in a channel, hence, substantially improve swing characteristics of the transistor and decrease the leakage current.
However, depending on the dimension of the fin active region, the threshold voltage is often difficult to control in fin FETs compared to a planar-type transistor. Furthermore, a leakage current is generated in an off state of the fin FET, and a gate induced drain leakage (GIDL) current and a junction leakage current are not distinctly improved compared to the planar type transistor and the recess type transistor.
Therefore, there is a need for nonvolatile memory devices that have a low off state leakage current and reduced short channel effect. In addition, there is a demand for a nonvolatile memory device having an excellent data retention time characteristics.